Four of the world’s leading chipmakers have now placed ASML’s roughly $400 million High Numerical Aperture extreme-ultraviolet systems on production road maps, turning a long-debated manufacturing technology into the semiconductor industry’s next shared platform. Intel is already using High-NA EUV on selected layers of commercial processors, Samsung Electronics and SK Hynix are targeting memory production in 2028, and Taiwan Semiconductor Manufacturing Co. says it plans to begin using the machines for advanced-node production in 2030.

The convergence matters because lithography determines how finely manufacturers can print the circuitry that gives modern chips their computing power. High-NA systems can resolve features about 40 percent smaller than today’s EUV machines, but they cost about twice as much, according to new Reuters reporting. The commitments indicate that leading manufacturers believe continued transistor scaling remains necessary even as they invest heavily in chiplets, three-dimensional stacking and advanced packaging.

They also deepen the technology sector’s dependence on a single European supplier. ASML has no commercial rival in EUV lithography, the process required for the smallest features in leading-edge logic and memory chips. That position gives the Dutch company unusual influence over the cost, timing and geographic distribution of the computing capacity behind artificial intelligence, smartphones, data centers and other high-performance systems.

Sharper optics reduce complex patterning steps

Lithography works by projecting a circuit pattern onto a light-sensitive coating on a silicon wafer. The minimum printable feature depends partly on the light’s wavelength and the numerical aperture of the projection optics, which describes how much of the light’s angular range the system can collect. Existing EUV scanners use a numerical aperture of 0.33. High-NA raises it to 0.55, allowing ASML’s EXE systems to target an optical resolution of 8 nanometers, according to the company’s product specifications.

That greater resolution can replace some multiple-patterning sequences in which manufacturers expose and process a wafer repeatedly to create one dense layer. Fewer steps can shorten production flows and reduce opportunities for alignment errors, although the economics depend on how many layers use High-NA, the scanner’s throughput and availability, and the yield of completed chips. A more capable machine does not automatically make a process cheaper when its purchase price is so much higher.

The optics themselves illustrate the difficulty. High-NA EUV uses mirrors rather than conventional lenses because EUV light is absorbed by air and most materials. The projection assembly contains more than 40,000 parts and weighs about 12 tons, while its mirror surfaces require subnanometer measurement, according to optics supplier ZEISS. That precision reflects why competitors that sell older deep-ultraviolet systems have not yet produced a commercial EUV alternative.

Intel supplies the first manufacturing evidence

Intel’s early deployment offers the clearest evidence that High-NA has crossed from experimental imaging into production. The company says it has processed more than one million wafers across tool certification, research and development, and volume manufacturing. High-NA is being used on selected layers for a subset of Core Ultra Series 3 processors, code-named Panther Lake, and Intel says overlay accuracy, throughput and equipment availability are meeting its expectations.

Those claims come from a joint company announcement rather than an independent audit, and the one-million-wafer total combines development work with production. It therefore should not be read as one million completed commercial processors. Even so, the use of the technology in high-volume manufacturing is a material step beyond demonstrations, and Intel says comparable layers made with its older 0.33-NA EUV platform meet or trail the performance of the High-NA versions. The detailed Intel disclosure gives rivals an operating benchmark they did not have when the first commercial system arrived in 2024.

Intel’s lead does not settle the business case for every manufacturer. Its strategy has included aggressive use of new manufacturing technology as it tries to rebuild its contract foundry business, while TSMC has remained competitive by extracting more from existing EUV tools. ASML said in May that the first chips made with High-NA systems were expected within months, but contemporaneous reporting noted that TSMC had questioned whether the $400 million price was justified for its near-term nodes.

Memory makers accelerate the adoption calendar

Samsung’s plan to introduce High-NA in high-volume dynamic random-access memory manufacturing by 2028 broadens the market beyond leading-edge logic. DRAM cells must become denser while preserving electrical performance and manufacturing yield, and Samsung says the improved resolution could simplify process flows as scaling becomes harder. Its announcement describes the move as the first disclosed plan by a memory producer to use High-NA in mass production.

SK Hynix has also set 2028 as its starting point, while Micron has ordered tools without announcing a production date. Memory chips are generally smaller than the largest processors used for AI, which can make High-NA’s reduced exposure field less restrictive. For ASML, adoption by memory manufacturers would diversify demand and increase the number of process layers that could use its most expensive scanners.

TSMC’s decision is slower but strategically significant because it is the world’s largest contract chipmaker and produces advanced processors designed by companies including Apple and Nvidia. TSMC now intends to use High-NA for high-volume manufacturing beginning in 2030 and expects the number of High-NA layers to rise as transistor architectures become more complex. Its formal commitment does not identify a specific node or guarantee the scale of deployment, leaving room to adjust the timetable as cost and yield data improve.

The mask format remains an industry bottleneck

High-NA’s optical design prints only half the field size of existing EUV scanners when used with the industry’s standard six-inch photomasks. Large chips can be divided into two exposures and stitched together, but stitching adds design, alignment and throughput challenges. Intel says customers can already use six-inch masks by arranging designs within the smaller field or using its stitching methods and process-design tools. Those workarounds make production possible, but they do not eliminate the long-term efficiency penalty.

ASML and TSMC therefore launched an industry initiative to develop six-by-12-inch masks, with a pilot line targeted for 2031 and full system readiness for advanced-node production in 2033. Larger masks would let a High-NA scanner expose a full-size field without stitching, potentially improving productivity and lowering per-chip costs. Samsung has joined the effort, and Intel and ASML say mask makers, automation suppliers, electronic-design companies and materials producers are participating in the broader ecosystem.

The long schedule shows why semiconductor manufacturing choices are made years ahead of product launches. A new mask size affects not only the scanner but also inspection equipment, materials, handling systems, design software and factory automation. The ASML-TSMC road map is consequently a coordination plan, not proof that the larger format will arrive on time or deliver every projected saving.

ASML’s leverage grows with industry alignment

ASML’s existing EUV systems, priced at about $200 million each, are nearly sold out through 2027, while artificial-intelligence demand has encouraged customers to seek more capacity. Reuters cited a JPMorgan estimate that ASML held 94 percent of the overall lithography market in 2025, with its share effectively complete at the EUV frontier. High-NA adoption could extend that dominance into the 2030s because every leading manufacturer must qualify the same core platform even while competing on process recipes, chip design and factory execution.

That concentration is both an industrial advantage for Europe and a supply-chain vulnerability. Each High-NA system depends on a specialized network that includes ASML’s Dutch manufacturing operations, ZEISS optics in Germany and numerous suppliers of lasers, metrology and precision components. Capacity cannot be expanded like ordinary electronics assembly, and export-control decisions involving advanced lithography can influence which countries are able to build leading-edge production.

The new commitments establish that High-NA is moving into the industry’s production plans; they do not establish that every chip layer will use it or that the economics will beat improved conventional EUV in every factory. The evidence to watch is operational: sustained wafer throughput, equipment availability, defect rates, yields and the number of exposures eliminated. Intel has supplied the first manufacturing-scale signals, while Samsung, SK Hynix and TSMC have supplied dates. Their results will determine whether ASML’s most expensive machine becomes a selective tool for a few critical layers or the defining lithography platform of the next decade.